A 250kS/s, 12-bit Column-Parallel Delta Sigma ADC for CMOS Image Sensors

Camera technology has significantly improved over the course of the last 30 years. Two of the current contributors in this technology are the Complementary Metal Oxide Semiconductor (CMOS) and Charge-Coupled Device (CCD) image sensors. The benefits of a CMOS system is that the entire camera can be manufactured on a single chip. This means that only a single fabrication run is needed, resulting in a smaller system and cheaper means of production. Additionally, CCDs continue to be used due to producing a slightly better image quality. However, as technology continues to improve the difference in the image quality decreases. In order to maximize the benefit of a CMOS image sensor’s lower footprint Analog to Digital Converter (ADC) designs need to be constructed and realized. 

For the I2Sense lab, this will be the first chip fabricated with an integrated ADC contained within the same chip as the image sensor.

During the process of determining the best architecture to use to meet the constraints provided for the project, the team came to the conclusion that the biggest consideration would be the amount of area used by the ADC. A Delta Sigma ADC was the best solution to meet the space and resolution requirements of the project. A brief overview of the system, what it does and how it operates, can be summarized as: 

• The Delta Sigma ADC takes in an analog voltage produced by the image sensor’s pixel and converts it to a Pulse Code Modulated (PCM) signal with the maximum sample rate of 1MS/s. For higher magnitude inputs, the pulse is 1 for more of the period and for lower magnitude signals, the pulse is 0 for more of the period. 
• The PCM signal is then sent to the Cascaded Integrated Comb (CIC) filter which down samples and averages the PCM by a factor of 512, producing one averaged output per 512 samples of the PCM signal, outputting it as a 12-bit number. 
• This 12-bit number is a digital representation of the voltage on the pixel. The stored voltages can then be used to recreate the image from the sensor, since the voltage on the pixel is related to the wavelength and intensity of light incident on the pixel. 

The design solution is developed in stages, with an initial logical description of the system being created in Simulink (Figure 1). From there, the analog side begins development in Virtuoso and the digital side using the Matlab Filter Designer tool to generate Register Transfer Level (RTL) code for the digital CIC filter. Vivado is then used to adjust the auto generated RTL code (Figure 2). At this stage the plan was to have the team break into different design methodologies for analog and digital. With the analog team continuing to develop the Delta Sigma ADC in Virtuoso and the digital team using the automated place and route of RTL code available for digital logic through Genus and Innovus. Due to complications, the digital library for the technology node was not received. Therefore, the digital team shifted to using the analog design flow in Virtuoso. From there, schematic descriptions of the design were created for the various components of the ADC and filter, the digital components are consistent with well documented designs of digital logic elements so the schematic views of digital subcomponents will not be posted (Figures 3 to 6). This was followed by schematics for the complete analog and digital sections (Figure 7 and 8). Finally, the positive output of the comparator is connected to the filter in of the digital filter. Multiple sets of iterations were done until performance specifications were met, allowing work to begin on layout. Shown in the photo gallery are some examples of subcomponent layout, the entire system layout is not human readable due to scale (Figure 9 and on). The team focused on starting with the subcomponents of each section and tiling the design together. Tiling the ADC with the filter was the last step. Once the layout is completed the design files will be sent for fabrication. 

The verification of the design solution, like the design itself, was completed in stages: 

1. The initial verification was completed using the logical model developed in Simulink. This gave the team an idealized view of the systems performance and a baseline to compare the actualized design to. 

2. The next stage initially differed for the analog and digital teams. After the logical performance was verified, the analog team began making subcomponent schematics in Virtuoso and simulating them with the Analog Design Environment (ADE). This gave non idealized views of the system behavior modeling the signal rise times, steady state errors, and a number of other performance issues not seen in the idealized logical view. 

3. The digital team at this stage used Vivado to generate a testbench and output the data generated by the RTL code to MATLAB to have its performance measured. This, however, didn’t account for physical effects of actual components, but allowed for better understanding of required clock timing and signal propagation requirements. The digital team would then have used automated tools to perform place and route after providing performance, power, and area constraints. After place and route, simulations would have been run on the various stages of the design using tools like Xcelium. Since the digital library wasn’t received, the verification was completed using the same process as the analog team. 

4. Schematic views of components were created for both the analog and digital sides and tested. Different configurations for the subcomponents were tested to find which best met the constraints with as little trade off as possible. As new constraints were discovered over the course of the design process, adjustments were made throughout the entire process. 

5. Subcomponents were connected and tested with other components in isolation of the rest of the system. These were then adjusted if unforeseen issues were present, and slowly the system began to come together as each level was verified. 

6. Due to time constraints, layout began before the full chip schematic simulations had been verified. Design Rule Check (DRC) was used to ensure manufacturability of layout and Layout Versus Schematic (LVS) was used to ensure the layout connections matched the schematic. Finally, post layout simulations were run to ensure added parasitic effects of layout didn’t drastically impact system performance. 

7. Complete schematic ADC simulations were run and verified in isolation of the filter. Complete filter schematic simulations were run and verified in isolation of the ADC. 

8. Complete system schematic simulations were run to verify performance when everything was connected. 

9. Layout of full filter and full ADC was completed and verified with DRC and LVS separately, and post layout simulations were conducted. 

10. After the final layout of the entire system was completed, tests were run, and performance was verified. 

The process of designing integrated circuits follows the design process outlined in What Makes Our Design Solution Effective, and once the design files are generated, they will be sent to a facility capable of manufacturing Integrated Circuit (IC) chips to be produced.