RF (Radio Frequency) Generator Controller

Currently, Acceleware have a controller design which uses a Dspace Field Programmable Gate Array Board with a remote desk that is expensive to maintain and provides the company with a software that has a steep learning curve. The design Acceleware had built was a piece of lab gear which required a full professional license to run and was deemed overkill in performance. Fortunately, the operating conditions of the generator changed slowly so not much signal processing was required to keep up, thus downsizing their design was ideal.

The design we have created provides Acceleware a solution which resolves the main pain points highlighted. With performance, our design provides adequate control and signal processing for their generator in real time. With time, our design provides well documented python and VHDL code that is extensible and easy to comprehend. With pricing, total hardware design was in the ballpark of ~500$ while all software written used open source libraries and was done on free platforms.

While our project does not make any groundbreaking advancements in FPGA and Raspberry Pi hardware design, we were required to reformat portions of our FPGA board as the manufacturer’s specifications did not match our design requirements. This allowed us to provide clean data samples from our generator which greatly improved our web server results. 

To provide more effective process management within the software design and the reception and transmission of controller data, curio a co-routine based library was implemented within our software base. This allows our software to handle every process in an asynchronous format which allows the management of both asynchronous requests such as communication to the generator in real time while allowing synchronous processes to run via a queuing system.

Furthermore, our design provides an effective platform for controller testing which can be easily re-built and replicated with commercially available hardware. 

Our design solution offers a simplistic yet extensible design which allows users of the device to replace the hardware components within set design limitations. This allows users to upgrade/side-grade existing devices while being able to use the same software design on the new platform with ease. Furthermore, our software is also designed with extensibility in mind to allow users to manipulate the sampled number/values.

To ensure our design was airtight, our group’s testing lead collaborated with our FPGA design lead and Python lead throughout the design process of each software module to ensure that they are functional and thoroughly tested with unit tests. Each piece of hardware was thoroughly researched and tested for functionality to ensure that they fit within the designed layout we had built. 

Further validation was done by providing transparency to our academic advisors and sponsors during our design process to ensure they understand where our design stands and provide feedback if necessary.

The design solution we have crafted during our first design review planned our intended timeline and scope of the capstone and ensured that each milestone would have leeway for possible scope creep, additions, or unintended circumstances. With that timeline set in stone, our design has been able to meet our requirements set for the minimum viable product along with various additions which our sponsor has agreed upon. The final product of our design will provide our sponsor with an extensible codebase and a remote user interface with in-depth documentation and functional pre-programmed hardware components.

The economic feasibility of this project has been taken into account as our total design cost has not exceeded our baseline comparison for designing the project. That baseline was the expected cost of purchasing a professional license of Matlab of $2711 cad (2150 usd). If replacements were necessary, each hardware asset which has been purchased by the group can be acquired via digikey.com and the software libraries used are all free to access.