Hardware Based Computational Accelerator

Our design is built to address issues of computation speed and throughput. Providing acceleration of computation is a primary concern for the industry. Aspects of our design, and the exploration it represents allow it address practical concerns for accelerating computation.

There are many practical limitations to accelerating computation. A big one is the feasibility and cost associated with the FPGAs used to develop acceleration solutions (>30,000 USD per board). Our design and implementation on AWS make the use and development of this accelerator much more practically feasible from a cost perspective for users.

In addition, because of the vendor-neutral (IP is open source) nature of the eBPF instruction set, and eBPF assemblers our processor can run programs from any variety of potential sources or use cases as imagined by the end user.

Also,  because of the open-source availability of our design and Eideticom’s approach to the project, our basic design can be used as a jump off point for other specific improvements and additions by other engineers in the industry.

The Hermes Accelerator contains an eBPF native processor. To our knowledge, a native eBPF processor has not been implemented before, yet due to the growing prevalence of eBPF there is already a healthy ecosystem that supports compilation for our architecture.

Future versions of the accelerator will contain multiple processors, allowing high levels of speed and parallel computation for general compute purposes. Our design allows access to this speed and parallelism while only requiring general programming knowledge, as the eBPF interface eliminates the need to learn specialized FPGA and AWS hardware design.

Our design is effective because it is an improvement on existing solutions. FPGAs are used to offload work to a custom circuit, while eBPF is used to describe the work that needs to be offloaded. By combining the two technologies we created a custom circuit that can dynamically take work from the host. The technologies already exist, we just combined them to create something with the characteristics of both.

Our eBPF native processor is fully effective at interpreting and executing eBPF programs and outputting results as expected. Our validation process was key to ensuring that our processor design was able to accurately and predictably run these programs.

The solution was rigorously evaluated using a complete set of test cases encompassing the entire eBPF instruction set. Each instruction was passed through the processor and each result was validated. All 111 instructions required by the sponsor, Eideticom, were successfully processed by the system and produced the correct result.

Testbenches for each subcomponent in the processor and for the processor as a whole were created to exhaustively test all aspects of the design, including edge cases, difficult scenarios, and maximum operating conditions. A total of 20 testbenches were created which support continuous integration testing in validating future improvements and modifications done to the processor or any of its underlying subcomponents. 

Using tests as developed by our team, and industry sources, we were able to verify communication between our custom designs on the FPGA card and the host system. For future progressions of the design this validation will be key to enabling communication between the host and our developed processor. 

Overall, these tests demonstrated and ensured that the project met the requirements for the eBPF instruction set, that its design and implementation is robust and operational, and that it is able to communicate with external drivers over a memory interface.

Based on the results of validating our project, we can say that although our design would work, it is likely not at the point where it would be an effective source of offloading computation. However, we know for a fact that this technology is used and is effective in the right circumstances. What needs to happen for our design to be completely feasible is improvements to the processor. If the processor can be designed to handle higher clock speeds up to viable computation speeds then this design would be a great way to offload computation and speed up tasks.

What we were able to show is that this is a booming branch of current technology and being a part of it, even if all we were able to accomplish was a proof of concept, was extremely interesting and there is a lot of future in designs like this.